Mask Layout Designer

Overview

Our teams are responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references. We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will work closely with the design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing our client’s state-of-the-art designs and getting them into hundreds of millions of products.

As an IC Layout Engineer, you will be a key member of our team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. 

Responsibilities: 

• Detailed transistor-level layout of RF and analog circuit blocks including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. 
• Block level layout through full verification flow including extraction, DRC, LVS, and DFM checking. 
• Co-work with designers on block level floorplanning. 
• Layout review for power/gnd routing, electromigration, signal path check, differential and IQ matching, and signal coupling.

Experience:

• BS and 5+ years of relevant industry experience.
• FinFet experience

Ideal Candidate:

• Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.
• Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.
• Solid understanding of RC delay, electromigration, and coupling.
• Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE, etc.
• High level proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc. in FinFet Technology (7nm experience highly preferred)
• Knowledge of CADENCE layout tools.
• Excellent communication skills and able to work with cross-functional teams.
• Scripting skills in PERL or SKILL are a plus, but not required.

The target hiring compensation range for this role is $68.48 to $76.09 an hour. Compensation is based on several factors including, but not limited to education, relevant work experience, relevant certifications, and location.

About Aquent Talent:

Aquent Talent connects the best talent in marketing, creative, and design with the world’s biggest brands.

Our eligible talent get access to amazing benefits like subsidized health, vision, and dental plans, paid sick leave, and retirement plans with a match. We also offer free online training through Aquent Gymnasium. More information on our awesome benefits! 

Aquent is an equal-opportunity employer. We evaluate qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other legally protected characteristics. We’re about creating an inclusive environment—one where different backgrounds, experiences, and perspectives are valued, and everyone can contribute, grow their careers, and thrive.

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